Generally, a bus arbiter assigns control of a bus to a single processor when one or more of the processors in a system attempts to access the system bus. This arbitration function is often referred to as assigning priority to an individual processor in the system.
One problem with prior art bus arbiters is that they are not equitable (i.e., some processors receive highest priority more often than others) when less than the designated maximum number of processors are operating in the system. For example, in a full four-processor roundrobin scheme with only three processors, assigned to numbers 0, 1, and 2, processor 0 would receive highest priority twice during each cycle, while processors 1 and 2 would receive highest priority only once.
Other problems exist in prior art bus arbiters. For example, a flip-flop is required for each processor. Also, non-requesting, slow-requesting or improper functioning processors are included in the arbitration function which can delay the entire system. Additionally, jumper wires or switches, which easily can be improperly set, are required to select the number of processors in the system.